1. Field of the Invention
The present invention relates to a method of fabricating a thin film transistor (TFT), and more particularly, to a method of fabricating a self-aligned TFT in which the structure thereof is fabricated in a self-aligned manner.
2. Discussion of the Related Art
In a large sized high-resolution TFT liquid crystal display, a self-aligned TFT is used as a pixel switching element to increase the aperture ratio and decrease the power consumption. The self-aligned TFT has a smaller overlap portion between the gate electrode and the source electrode than a conventional inverse staggered TFT. Thus, for a fixed channel width-to-length ratio (W/L), parasitic capacitance Cgs of the self-aligned TFT is smaller than that of the inverse staggered TFT. Pixel voltage shift level .DELTA.Vp, which causes flickers and gray level errors, is proportional to parasitic capacitance Cgs. Accordingly, it is important to decrease the parasitic capacitance Cgs in order to reduce pixel voltage shift level .DELTA.VP.
If the self-aligned TFT having a smaller pixel voltage shift level .DELTA.Vp is used as a pixel switching element, the aperture ratio can be improved and power consumption is decreased. Furthermore, with the self-aligned TFT, process tolerance does not affect its fabrication, and accordingly, it is possible to manufacture a TFT that has a very short channel. The shorter channel length requires smaller drain-source current Ids to charge a capacitor. Thus, the channel width can also be decreased with the reduction of the channel length since drain-source current Ids is proportional to W/L. This further decreases parasitic capacitance Cgs. For reference, parasitic capacitance is proportional to W(L/2+.DELTA.L), where .DELTA.L is an overlap length, a constant.
FIGS. 1A to 1F are cross-sectional views showing a conventional method of fabricating a self-aligned TFT. Referring to FIG. 1A, a conductive material, such as Al or Cr, is deposited on a glass substrate 10, and patterned to form a gate electrode 11. Referring to FIG. 1B, a silicon oxide layer (SiO.sub.2) and/or silicon nitride layer (Si.sub.3 N.sub.4) is deposited on the overall surface of the glass substrate including gate electrode 11 to form a gate insulating layer 12 in a single- or double-layered structure. An amorphous silicon is deposited on gate insulating layer 12 to form an active layer 13. Thereafter, a silicon oxide layer, silicon nitride layer or insulating layer is formed on a predetermined portion of active layer 13 to form an ion-implantation stop layer 14.
In forming the above structure of ion-implantation stop layer/active layer/gate insulating layer, the silicon oxide layer (or silicon nitride layer), amorphous silicon layer, and the insulating layer (silicon oxide layer, silicon nitride layer, or insulating layer having photosensitivity) are sequentially formed, and the insulating layer and amorphous silicon layer are patterned. Here, in patterning the ion-implantation stop layer, a photolithographic process is performed by exposing a photoresist or the insulating layer having photosensitivity from the backside of the glass substrate 10 using gate electrode 11 as a mask. Referring to FIG. 1C, ion shower doping is performed to the exposed portions of active layer 13 to form shallow n.sup.+ regions. Referring to FIG. 1D, a metal layer 15 for forming a silicide, such as W or Mo, is deposited on the entire surface of the glass substrate 10 including ion-implantation stop layer 14, portions of active layer 13a in which the n.sup.+ regions are formed, and exposed portions of gate insulating layer 12.
Referring to FIG. 1E, annealing is carried out to form a silicide layer 16 at the interface between the metal layer and the portions of active layer 13a in which the n.sup.+ regions are formed. The metal layer 15 remains unchanged on the other regions. Subsequently, the metal layer 15 is etched. Since the metal has etch selectivity to silicide, silicide layer 16 formed on active layer 13 a remains as it is when etching the metal. Referring to FIG. 1F, a metal, such as Al or Cr, is deposited on the overall surface of the glass substrate 10, and selectively removed to form source and drain electrodes 17, 18 contacting silicide layer 16 on the respective sides.
The above-described self-aligned TFT fabrication method requires more masks than a conventional TFT fabrication method, resulting in a complicated manufacturing process. Furthermore, since exposure is performed from the backside of the glass substrate in a self-aligned manner to form the ion-implantation stop layer, longer exposure time is necessary, and accordingly, throughput is sacrificed.
To form a perfect silicide layer, the annealing should be carried out at a temperature of above 600.degree. C. When the self-aligned TFT is applied to a liquid crystal display, silicide cannot completely and uniformly be formed, since the upper limit in processing temperature exists when using a glass substrate. Thus, it is difficult to achieve uniform characteristics of TFT over the entire area of the substrate. In the case of a quartz substrate, the formation of perfect silicide layer is possible but fabrication cost becomes high.
Moreover, as shown in FIG. 2, because the n.sup.+ region is formed on the active layer using ion shower doping, its resistance is larger than that of a normal n.sup.+ -amorphous silicon layer. Accordingly, the n.sup.+ regions act as series resistors during the device operation. These series resistances affect the measured effective mobility of the amorphous silicon forming the active layer. The effective mobility can be calculated using a current relation formula modified according to the resistance of the n.sup.+ regions, as follows: ##EQU1##
Where, .mu. is the effective mobility to be measured, .mu..sub.0 is the mobility of amorphous silicon TFT itself, R.sub.s is the series resistance of n.sup.+ regions, W/L is ratio of channel width W to channel length L, V.sub.G is the gate voltage, and V.sub.T is the threshold voltage of the TFT. As shown in formula (1), the measured mobility .mu. decreases as the channel length L becomes shorter. FIG. 3 is a characteristic graph showing the relation between the channel length and the measured mobility. This shows how mobility .mu..sub.lin in the linear region and mobility .mu..sub.sat in the saturation region decrease with the channel length L (Ion dose 1.times.10.sup.16 cm.sup.-2 in n.sup.+ region, channel width W=40.mu.m). So, the charging cannot be improved as much as inversely-proportional to the channel length.